Hi,

I read the paper, "Predicting the Phase Noise and Jitter of PLL-Based Freqeuncy Synthesizers". The behavioral codes about blocks of PLL was very helpful for me.

However, I cannot apply the simulation results to behavioral parameter, such as Kdet (equation 66). (Kdet=Imax? or average value of PSS simulation result?)

Can you give me some example about extracting PFD/CP and Divider jitter such as chapter 10.1.1 (extracting accumulating jitter of VCO)?

Thanks.