Question 2:  No problem (probably).  People put MIMs on top of MOS caps all the time.  A few processes don't allow diffusion on MIM so check your design rules.

Question 1: 1 nF is probably not practical.  There are two schools of thought for ADC reference design.  Either a) you make the reference super-duper low impedance so that the delta-q from the ADC isn't enough to move the reference more than an LSB/2.  Or, b) you can make a fast reference buffer that recovers before the next sampling event.

Typically people use a) if they can put the decoupling (or at least most of it) off chip.  Beware the bondwire inductance if you do this.

People typically use b) when they need an internal reference decoupling.  The downside is you need to design a fast, low-impedance buffer (typically class A/B).

You can spec out your buffer by calculating the current it will need to supply to the reference node.  Figure out the worst cast delta-Q (based on your reference voltage and your cap sizes) and then use the sampling period (your delta-t) to calculate current requirements (delta i = (delta Q)/(delta t))

Good luck!

PS I thought you were working on a pipelined ADC?

Hi carlgrace,


I've done some more analysis, and regarding option a) I came to a weird conclusion regarding the decoupling capacitance. The conclusion is, "if you want to decouple the reference, you need a huge capacitance. If you aren't willing to put that much decoupling capacitance, then its better not to have any decoupling capacitance at all." The reason is that when you add decoupling, the time-constant of the on-chip reference increases. Since it takes longer to settle, you have to make sure the initial spike in the reference voltage is less than 0.5 LSB.

I reached this conclusion after simulating a series RLC with a damping factor of 1. I swept the value of the capacitor, and checked how long it takes to settle to within 12b resolution.

I'm not sure if this is what you meant by "Typically people use a) if they can put the decoupling (or at least most of it) off chip." The problem with this method is that my circuit would be more sensitive to any other noise...


thanks,
Aaron

thanks!

Aaron

Aaron,

You're right that not putting enough decoupling capacitance won't help you much.  But believe if you don't put any at all you'll be sorry!  If you can't (or don't want to) put enough capacitance on the chip, go for method b.

People often try to just put a huge cap off chip and forget about it.  This sometimes works but if your ADC is fast the bondwires will kill your reference settling.  Even though the caps are low impedance the bond wire becomes higher and higher impedance.

Here's the schematic

aaron_do wrote on Feb 3^rd, 2014, 10:34pm:
Aaron,
I meant that if you do a conversion, there will be more than on spike on Vref: so you may need to look at the settling behavior of Vref wrt. spikes over time with several pulses [or even conversions] (depending on use case [e.g. discontinuous operation], loading vs. drive strength, gain, ...).
- B O E