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on current reduces below e-11 when interface trap is introduced (Read 3704 times)
biju4u90
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on current reduces below e-11 when interface trap is introduced
Feb 07th, 2014, 11:38am
 
why the on current reduces to e-11 order from e-6 order when an interface trap level is introduced in SiC power mosfet??
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Geoffrey_Coram
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Re: on current reduces below e-11 when interface trap is introduced
Reply #1 - Feb 25th, 2014, 12:52pm
 
I don't think you've given us enough information to understand your question.  Are you talking about introducing an interface trap level in the device model for the mosfet?  or doing something in the fabrication of the device?
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biju4u90
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Re: on current reduces below e-11 when interface trap is introduced
Reply #2 - Mar 9th, 2014, 9:07pm
 
Yes. The problem occured while trying to introduce interface traps in mosfet. its not fabrication, just simulation using atlas
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biju4u90
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Re: on current reduces below e-11 when interface trap is introduced
Reply #3 - Mar 9th, 2014, 9:08pm
 
is there any limitation for the oxide thickness that can be used while introducing interface traps in a mosfet simulation?
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