Kamal Mustafa
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Posts: 3
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Hello everyone,
New to the Forum :). I have registered here because I have heard that there are lots of talented PLL designers in the forum. Maybe this is a great opportunity to learn quality information from you :)
To begin with, I have started recently learning PLL design. The first software to stumble upon was Cppsim. The software is easy to understand and use. However, the tutorials posted on the official website use an outdated version (Cppsim 3). Anyway, when following the tutorial steps, different results and warnings appear.
In the file attached is the fractional-n frequency synthesizer system level design and two plots. Although I followed the required steps, the 'vin' appears as shown in 'My vin' plot. Unfortunately, the tutorial shows 'tut plot'. Vin is the dc used to steer the VCO.
In addition i receive these warnings:
'Warning in Vco.inp: divide_val is too small for the given sample rate! in this case, divide_val = '2', and should be >= '8' -> setting divide val to '8' whenever it is too small Warning in Vco.inp: interpolated output has value beyond -1 to 1 range in this case, out = -5631.416 probable cause: input or divide value inappropriate in this case, in = -18.051, divide value = 32 also, make sure divide value is not changing more than once per VCO cycle Warning in EdgeDetect.inp: in is < -1.0 or > 1.0 in this case, in = -5631.416 warning in 'delay.inp': nonvalid input! in must -1.0, 1.0, or some value inbetween in this case, in = -5.631e+003 **** in short, input is not conforming to the double_interp protocol **** warning in Vco.inp: divide value transitioned more than once during one cycle of Vco output'
Finally, it is important to state that the EMACS file is exactly written as the tutorial instructs.
I would be thankful for any thoughts and ideas.
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