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aaron_do

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recommended phase margin for VCO LDO
Mar 07^th, 2014, 12:53am

Hi all,

I was wondering how much phase margin I need for my VCO's LDO. I originally designed for about 75 degrees, but now I'm thinking I should give a lot more headroom. i.e. around 90 degrees or more if possible. The problem is I've noticed some VCO spurs which occur right around the unity-loop-gain frequency of my LDO. I'm thinking its because the VCO periodically draws current from the LDO (even harmonics mainly), and due to insufficient phase margin, this might be causing some ringing on the LDO output.

Does anybody think this is a likely cause, and can anybody provide a rule of thumb for how much phase margin we normally need for a VCO's LDO?

thanks,
Aaron

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carlgrace

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Berkeley, CA

Re: recommended phase margin for VCO LDO
Reply #1 - Mar 7^th, 2014, 3:59pm

I'm sure you're using a differential VCO, right? The variation in current you are seeing should be tiny and therefore the LDO should be able to settle quickly. As long as the LDO is bypassed correctly those little current pulses should be supplied by the bypass cap.

I just checked my last PLL and the LDO VCO has a phase margin of over 80 degrees during normal operation so you may be on to something... Usually a VCO doesn't draw more than a few mA so it shouldn't be too hard to make a really big phase margin on your LDO.

One tricky thing with VCO LDOs to watch out for is their stability at start up. The VCO will typically come up in a low or no current state (before the startup circuit kicks in) and make sure your LDO isn't oscillating at this point.

BTW The easiest way to increase the phase margin is to increase the dropout voltage (so you can shrink the pass device).

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aaron_do

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Re: recommended phase margin for VCO LDO
Reply #2 - Mar 9^th, 2014, 6:24pm

Hi carlgrace,

thanks for the reply. Yes its a differential VCO...

Quote:

BTW The easiest way to increase the phase margin is to increase the dropout voltage (so you can shrink the pass device).

I think that would be true if my output was the dominant pole, but it seems that the design I inherited has an internal dominant pole. There is no additional capacitance at the output (I believe now that this is the main issue), so now I'm worried that the design will have trouble when the load current has sudden changes. The problem is, if I want to have the output as the dominant pole, it will need a lot of additional capacitance. Maybe I should add a reasonable amount of output capacitance, but keep the internal dominant pole and just shift it lower.

thanks,
Aaron

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aaron_do Senior Fellow Offline Posts: 1398	Re: recommended phase margin for VCO LDO Reply #3 - Mar 14^th, 2014, 12:39am Arghhhh, I finally figured out the problem. There was a roughly 92 MHz periodicity to the jitter, and after pick apart my PLL piece by piece, I found that it was some odd harmonic of the strobe period in my transient analysis setup! Aaron
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