leon_O
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Posts: 6
Chennai
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The output of the first stage is very small compared to that of the second stage. So, voltage across C_c is approximately output voltage. When I5 flows through this capacitor, output voltage ramps up/down with slope I5/C_c. I5 is the maximum source/sink current from the first stage which flows through C_c. The assumption that I7>>I5 is there because the slew rate is not limited by the second stage current.
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