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Mikay

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SHA Reference Voltage Buffer
May 23^rd, 2014, 8:07am

Hi everyone,

I have a basic question for the pipeline ADC Sample and Hold amplifier design. The attached is the charge transfe SHA. VCM1 is directly connected to the OTA input and the bottom plate of the sampling capacitors. Generally speaking, if the input signal is fully differential the current sinking or sourcing to the node VCM1 is very small. However, when the input signal is just single ended, there will be large transcient sink or source current to this node during sampling phase. So the node VCM1 should be of a very low impedance node. That is to say, we may need some kind of buffer to driver this node, but It's quite strange to me people hardly talked about this. . Anyone has design experience with this?

warm regards,
-Mikay

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Mikay

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Re: SHA Reference Voltage Buffer
Reply #1 - May 25^th, 2014, 6:06am

Hi everyone, My question is actually how to drive the common mode node VCM1 and VCM2? Do I need another two buffers?

Thanks,
Mikay

Mikay wrote on May 23^rd, 2014, 8:07am:

Hi everyone,

I have a basic question for the pipeline ADC Sample and Hold amplifier design. The attached is the charge transfe SHA. VCM1 is directly connected to the OTA input and the bottom plate of the sampling capacitors. Generally speaking, if the input signal is fully differential the current sinking or sourcing to the node VCM1 is very small. However, when the input signal is just single ended, there will be large transcient sink or source current to this node during sampling phase. So the node VCM1 should be of a very low impedance node. That is to say, we may need some kind of buffer to driver this node, but It's quite strange to me people hardly talked about this. . Anyone has design experience with this?

warm regards,
-Mikay

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cchen

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Re: SHA Reference Voltage Buffer
Reply #2 - May 29^th, 2014, 10:53pm

Hi Mikay,
It seems that a buffer is needed for VCM1. Since the output of opamp is differential, buffer is not needed for VCM2.

Regards,
cchen

Mikay wrote on May 25^th, 2014, 6:06am:

Hi everyone, My question is actually how to drive the common mode node VCM1 and VCM2? Do I need �another two buffers?

Thanks,
Mikay

Mikay wrote on May 23^rd, 2014, 8:07am:

Hi everyone,

I have a basic question for the pipeline ADC Sample and Hold amplifier design. The attached is the charge transfe SHA. VCM1 is directly connected to the OTA input and the bottom plate of the sampling capacitors. Generally speaking, if the input signal is fully differential the current sinking or sourcing to the node VCM1 is very small. However, when the input signal is just single ended, there will be large transcient sink or source current to this node during sampling phase. So the node VCM1 should be of a very low impedance node. That is to say, we may need some kind of buffer to driver this node, but It's quite strange to me people hardly talked about this. . Anyone has design experience with this?

warm regards,
-Mikay

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RobG

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Bozeman, MT

Re: SHA Reference Voltage Buffer
Reply #3 - May 31^st, 2014, 9:01pm

It really depends on your individual circuit's speed and accuracy requirements. You can usually get away with a voltage divider or a diode connected device or a simple buffer.

Mikay wrote on May 25^th, 2014, 6:06am:

Hi everyone, My question is actually how to drive the common mode node VCM1 and VCM2? Do I need �another two buffers?

Thanks,
Mikay

Mikay wrote on May 23^rd, 2014, 8:07am:

Hi everyone,

I have a basic question for the pipeline ADC Sample and Hold amplifier design. The attached is the charge transfe SHA. VCM1 is directly connected to the OTA input and the bottom plate of the sampling capacitors. Generally speaking, if the input signal is fully differential the current sinking or sourcing to the node VCM1 is very small. However, when the input signal is just single ended, there will be large transcient sink or source current to this node during sampling phase. So the node VCM1 should be of a very low impedance node. That is to say, we may need some kind of buffer to driver this node, but It's quite strange to me people hardly talked about this. . Anyone has design experience with this?

warm regards,
-Mikay

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Mikay

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Posts: 35

Re: SHA Reference Voltage Buffer
Reply #4 - Jun 1^st, 2014, 3:38pm

Thanks Rob, If system need12bit accuracy with 50Mhz sampling frequency. dou you think a simple buffer is enough. How to decide the the speed of the buffer. Is it necesarry to bypass the buffer with a large capacitor? I have no any pipeline ADC design experience. If the the accuracy is just 10bit, is the requiremnet different for the buffer design?

Hi cchen,

If there is no buffer for VCM2, the node(feedback capacitor bottom plate) experiencing voltage variation may make the OPAMP input shifted from VCM1, thus requiring wide input comon mode range. I think it is reasonable to connect the nodes to the OPAMP output. How do you think of this?

warm regards,
Mikay

RobG wrote on May 31^st, 2014, 9:01pm:

It really depends on your individual circuit's speed and accuracy requirements. You can usually get away with a voltage divider or a diode connected device or a simple buffer.

Mikay wrote on May 25^th, 2014, 6:06am:

Hi everyone, My question is actually how to drive the common mode node VCM1 and VCM2? Do I need �another two buffers?

Thanks,
Mikay

Mikay wrote on May 23^rd, 2014, 8:07am:

Hi everyone,

I have a basic question for the pipeline ADC Sample and Hold amplifier design. The attached is the charge transfe SHA. VCM1 is directly connected to the OTA input and the bottom plate of the sampling capacitors. Generally speaking, if the input signal is fully differential the current sinking or sourcing to the node VCM1 is very small. However, when the input signal is just single ended, there will be large transcient sink or source current to this node during sampling phase. So the node VCM1 should be of a very low impedance node. That is to say, we may need some kind of buffer to driver this node, but It's quite strange to me people hardly talked about this. . Anyone has design experience with this?

warm regards,
-Mikay

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RobG

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Bozeman, MT

Re: SHA Reference Voltage Buffer
Reply #5 - Jun 2^nd, 2014, 8:18am

Mikay wrote on Jun 1^st, 2014, 3:38pm:

Thanks Rob, If system need12bit accuracy with 50Mhz sampling frequency. dou you think a simple buffer is enough. How to decide the the speed of the buffer. Is it necesarry to bypass the buffer with a large capacitor? I have no any pipeline ADC design experience. If the the accuracy is just 10bit, is the requiremnet different for the buffer design?

I reread and see you doing single ended so you'll need something decent. It is a space/time/power continuum. If you have a lot of space you can bypass a diode connect device. If you have a lot of time you can design a two stage buffer. If you have a lot of power you can use a diode connected device biased high enough that it settles each period. If you are getting paid by the hour you can do a meticulous investigation of all three and pick the best (just kidding).

You'll probably want ~Vdd/2 for VCM2. I recently realized this by splitting the feedback cap into two parts and then connecting one to Vss and one to Vdd. When you short them together you get (Vdd-Vss)/2. However, you may need to generate a Vdd/2 for the center point of the references so it will be easiest to buffer that. I'd use the same buffer as the reference and then if there is time you can optimize it.

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Mikay

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Re: SHA Reference Voltage Buffer
Reply #6 - Jun 2^nd, 2014, 10:52am

Thanks! Rob. Your comment is extremely useful to me!

For the VCM2, your design method is very good. The feedback capacitor being connected to VDD and GND is equivalent to buffering VDD/2 to these nodes while keep the input of the OPAMP unchanged for hold phase. Thanks. I will use a simple class AB buffer with bypass capacitor for my design. Adtionally,I will reserve an alternative pad for test(with an off-chip buffer). By this I will know how the buffer have effect on the overall pipeline ADC performance. Some documents(as followed) concludes the buffer will degrade SAR ADC accuracy as well as noise.

http://www.ti.com/lit/an/slyt355/slyt355.pdf

Thanks:)

RobG wrote on Jun 2^nd, 2014, 8:18am:

Mikay wrote on Jun 1^st, 2014, 3:38pm:

Thanks Rob, If system need12bit accuracy with 50Mhz sampling frequency. dou you think a simple buffer is enough. How to decide the the speed of the buffer. Is it necesarry to bypass the buffer with a large capacitor? I have no any pipeline ADC design experience. If the the accuracy is just 10bit, is the requiremnet different for the buffer design?

I reread and see you doing single ended so you'll need something decent. It is a space/time/power continuum. If you have a lot of space you can bypass a diode connect device. If you have a lot of time you can design a two stage buffer. If you have a lot of power you can use a diode connected device biased high enough that it settles each period. If you are getting paid by the hour you can do a meticulous investigation of all three and pick the best (just kidding).

You'll probably want ~Vdd/2 for VCM2. I recently realized this by splitting the feedback cap into two parts and then connecting one to Vss and one to Vdd. When you short them together you get (Vdd-Vss)/2. However, you may need to generate a Vdd/2 for the center point of the references so it will be easiest to buffer that. I'd use the same buffer as the reference and then if there is time you can optimize it.

Back to top

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