Mikay
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Thanks Rob, If system need12bit accuracy with 50Mhz sampling frequency. dou you think a simple buffer is enough. How to decide the the speed of the buffer. Is it necesarry to bypass the buffer with a large capacitor? I have no any pipeline ADC design experience. If the the accuracy is just 10bit, is the requiremnet different for the buffer design? Hi cchen, If there is no buffer for VCM2, the node(feedback capacitor bottom plate) experiencing voltage variation may make the OPAMP input shifted from VCM1, thus requiring wide input comon mode range. I think it is reasonable to connect the nodes to the OPAMP output. How do you think of this? warm regards, Mikay RobG wrote on May 31st, 2014, 9:01pm:It really depends on your individual circuit's speed and accuracy requirements. You can usually get away with a voltage divider or a diode connected device or a simple buffer. Mikay wrote on May 25th, 2014, 6:06am:Hi everyone, My question is actually how to drive the common mode node VCM1 and VCM2? Do I need another two buffers? Thanks, Mikay Mikay wrote on May 23rd, 2014, 8:07am:Hi everyone,
I have a basic question for the pipeline ADC Sample and Hold amplifier design. The attached is the charge transfe SHA. VCM1 is directly connected to the OTA input and the bottom plate of the sampling capacitors. Generally speaking, if the input signal is fully differential the current sinking or sourcing to the node VCM1 is very small. However, when the input signal is just single ended, there will be large transcient sink or source current to this node during sampling phase. So the node VCM1 should be of a very low impedance node. That is to say, we may need some kind of buffer to driver this node, but It's quite strange to me people hardly talked about this. . Anyone has design experience with this?
warm regards, -Mikay
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