HI guys

i wanna design Frequency Synthesizer.when i design VCO,for OSC Resonance i constrained chose over 750 ohm Resistor.
in you're opinion,my design is valid?

i'm so sorry loose-electron...
i try to edit my question

Hi aaron_do

yes,i know this resistance it's parasitic model for tank.
but,in you're opinion i can build an tank with 750 ohm resistance(parasitic model)?
at RLC parallel tank:

R=[√(L/C)]*Q      >>>>                (L=1nH , C=10fF)

the formula illustrate for have R=750 must Q is high!!

you think i can build the this tank??

ok ,i working at CMOS-90nm Technology
VCO tuning range is 5GHZ-10GHZ then C capacity is vicinity 40fF-10fF
and i simulate the design and calculate Q
Q is 4-6.66

with this Q i can't design an Tank with 750 ohm loss
nonetheless,in you're opinion i can use a real Resistance in Tank for post layout simulation?

tnx a lot sir loose-electron.
how i can set parasitic for every node in system?
my software is cadence.

Since you know what post-layout simulation is, you know how to get the parasitics at all the nodes. However, you need some way to extract inductance too. Try an EM simulator like ADS momentum. As loose-electron implied, if you model the inductor as just an ideal inductor with a parallel resistance at that frequency, your results will be wrong.


regards,
Aaron

Suggest that you talk with your design team locally about getting better models. Everybody sets up their model sets differently so you need to contact whoever is responsible for the design tools and semiconductor models that you are using

Hi,


Quote:


after creating your layout, you need to create an extracted model using Calibre or Assura. But you need to design the inductors separately using an EM simulator.

Actually these are the something like the basics of using the software, and it would be better if you could find somebody in your own lab who can go over this with you (I'm assuming you're doing this at a University).


regards,
Aaron