Hi,
I am getting some problems relating to input impedance matching.
Please help me with questions in the picture. Thank you.

Thank you, Aaron! I need to read it more before replying.

According to the analysis, Zin doesn't depend on output network at all.
I will simulate to check it now.

Hi baab,


1. Do it iteratively. For example, start off with a reasonable estimate for the output matching network, and then do input matching, and then adjust your output matching network again, and finally readjust your input matching network. It will only take one or two iterations depending on how good your initial estimates are.

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2. This statement is incorrect. S₁₁ is the input reflection coefficient when there is no reflection at the load. i.e. Γ_L = 0. Cadence doesn't need to know the details of your circuit. Note that Z₁₁ is measured with Z_L = ∞. i.e. Γ_L = 1.


regards,
Aaron

Hi baab,


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Nope.

You seem to be confusing the output and the load. Don't worry, everybody has this confusion when they are starting out. The output impedance is looking from the 50-ohm load back into the circuit. It is basically a parallel combination of your transistor output impedance and the inductor's impedance. The load impedance is the next circuit block. For example, in your case it is probably a mixer. In textbooks, the load impedance is set to 50-ohm, but in practice there is no such requirement.

It might help if you imagine that there is a transmission line connected between the source and the DUT, and the DUT and the load. Like so,

R_S ------tline (Z₀₁)------DUT------tline (Z₀₂)------R_L

Here is the sequence of events from the output side:
t1: DUT generates output wave on tline (Z₀₂)
t2: output wave reaches load. For  Z_L = Z₀₂, R_L = 0 and therefore there is no reflection (end - this is the case for S₁₁ analysis), otherwise go to t3.
t3: there is some reflection at the load (Γ_L), and this travels backwards down the tline (Z₀₂) to the DUT output.
t4: upon reaching the DUT output, there is some transmission back to the input (S₁₂), and if Z_out ≠ Z₀₂, there is some re-reflection.
t5: so this basically goes on for ever with the signal getting smaller and smaller as it is absorbed by all the loss and load.

In reality, the reflection coefficient should be defined wrt the transmission line since reflection is only a meaningful concept when the distance traveled by the signal is long enough for it to experience a time delay. So in this case, the load reflection coefficient would be defined by the mismatch between Z₀₂ and R_L.

However, for spectre's SP analysis, Z₀₂ is actually defined by R_L. Therefore Γ_L in the simulation is by definition equal to zero. So if you were to use a 1-kohm impedance for the load port, then for S₁₁, the load would be 1 kohm, but for Z₁₁, it would be infinite. A good reference if you want to understand this properly is "Power Waves and the Scattering Matrix" (I'm just quoting that from memory, so you'll have to look around"). Its quite an old paper.


regards,
Aaron

I inserted a output matching network between the output of transistor and the output port.
Let's call input reflection coefficients, S11 and S'11 correspond with two cases, before and after adding output matching network, respectively.

From measurement, I see that S'11 is different from S11.
And as I know, we can convert S11 and S'11 to Zin.
S11 is NOT equal S'11 and this means that Zin also changes as output matching network is added.

I am wondering why that is the case. Why Zin is affected by output matching network?
There is little feedback here.
(I suppose this is correct because the cascode topology is used.)
From the circuit, Zin only depends on Ls, Lg, Cgs, and gm.
Could you explain?

Hi, Aaron.

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I plotted S11 in smith chart and then move the pointer over the point and read that corresponding impedance value. I think that is Zin of the circuit with the condition there is no reflection from load.

I also used ZM analysis to find Zin and the two methods give the same result.

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No, Z11 is the input impedance as load is open, RL = ∞ while Zin here is measured as there is no reflection from load.

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It is very large.

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I haven't measured it yet. I was only interested in S11 and S22.
I thought that the cascode topology will always give good isolation or very small S12 no matter how good the input/output matching is.

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I don't understand why Zin changes largely as output impedance matching is added.
I supposed it should be very small change.

Thank you, Aaron.

Here is my circuit for simulation and simulation results.

1. Before adding output matching network
Zin = ZM1 = 109.1 - j 33.01
S11 = -7.604dB
S22 = -1.739dB
2. After adding output matching network
Zin = ZM1 = 50 - j5.711*10^-4
S11 = -99.19dB
S22 = -12.43dB

As you can see, S22 is not so good. Therefore, I did output matching again but after getting good S22, S11 is very bad. It is about -2dB.