fgcsk
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Is there any way to have a fixed time step in Verilog-A? I know $bound_step can limit the time step to a certain amount, but it does not guarantee the time step is fixed if I understand correctly.
Actually I just want to implement something like this: Y = Y + dYdt*timestep
I know Y=idt(dYdt, 0) can do it, but at some events I also need to directly modify Y, and idt() is an analog operator that is not allowed to do so. Any suggestions?
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