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settling time simulation of an op amp (Read 212 times)
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settling time simulation of an op amp
Dec 02nd, 2014, 11:55am
I've designed a sigle stage folded cascode op amp. I wanted to simulat it's settling time then  I went through the internet , all analog design books such as razavi , gray , johns & martin , bakers and papers and other literatures and I know all about the linear settling time and nonlinear one and etc , but now I am a little bit confused and I don't know which settling time ( small signal or larg sinal ) matters more in  practical applications? none of the above mentioned references made it clear. more papers and books just mentioned the small signal settling time . but  I don't know exactly which one has to be considered?
my second question is about the load cap . since my op amp is the single stage one thus I've used the load cap as the compensation cap.  In unity gain configuration we employ a load cap. In my case the load cap in unity gain config has A value of .5P and for compensation a smaller value comparing to the .5pf . my question is do I have to include this load cap ( compensation one which is smaller than the unity gain load cap ) in my  settling time simulation , which means two load cap together, or not?
considering the fact that  the compensation load cap has a smaller value and if we don't include it , doesn't introduce any stability issues , is the unity gain config cap enough for simulating  it ?
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Re: settling time simulation of an op amp
Reply #1 - Dec 11th, 2014, 8:26pm

  For settling time, the question is relatively straightforward. In your
application what is the largest positive step, what is the largest negative
step that the amplifier needs to perform. From here it get a little
complex since there are many ways to define settling, again use
definition that suits your application. That is when designing a
commodity op-amp and designing an op-amp for a pipeline ADC
what the circuit needs to do is different so the measurement may
details may change.

you might measure settling time to an absolute value, settles to
within +/- 1mV in xx nanoseconds or as percent of full scale, settles
to within +/- 0.1% in yy nanoseconds. For ADC designers, %
of full scale is easier to convert into lsbs. For commodity products
mV may be fine.

1) use a pulse source and apply a step that will drive the output
   from a maximum (minimum) to a minimum (maximum)
2) reference point is the zero crossing time of the input
3) Measure when the output settles to within a region you have
   defined as settled: mV, %, ...
4) Take the difference between #3 and #2, this is the settling time

Don't understand the load cap question, since you have not mentioned
assuming that you actually have a transconductance amplifier, no
output buffer. In real world you will always have load capacitance
so it needs to be considered separately from the capacitors that
determine the gain, i.e., you need to include both

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Re: settling time simulation of an op amp
Reply #2 - Apr 2nd, 2015, 3:37am

if you have a multi-stage op-amp than analyzing effect of comp-C and load-C is very important. A simple one stage op-amp is usually much more stable and behaves close to an RC lowpass of 1st order.
Maybe give us some screenshots of the circuit + plot of AC gain + phase vs f?
To match tran & AC results you have to use small pulses to not run into slew limits!
Checking for unity-gain (so full feedback) is usually the worst-case for stability, so you should be on the safe side.

Bye Stephan
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