cktdesigner
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Posts: 38
India
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Hi,
I am trying to check whether my dual-modulus prescaler (divide by 2 or 3) is working correctly. It is comprised entirely of models and no circuit elements.
I am using IC615 and AMS Simulator to do this check by running a transient analysis to do this check.
The schematic of of the the circuit is attached.
This is just the circuit given in Razavi's book (2nd Edn.) RF Microelectronics. The original circuit is also attached for your reference.
The test-bench I am using to test the circuit is also attached.
Code for the D-FF is as follows: `include "constants.vams" `include "disciplines.vams"
module adff (q, qb, clk, d);
output q; voltage q; // Q output output qb; voltage qb; // Q bar output input clk; voltage clk; // Clock input (edge triggered) input d; voltage d; // D input
real td; real tt; real vh; real vl; real vth; integer dir;
real state;
analog begin td = 0; tt = 0; vh = 1; vl = 0; vth = (vh + vl)/2; dir = +1; @(cross(V(clk) - vth, dir)) state = (V(d) > vth); V(q) <+ transition( state ? vh : vl, td, tt ); V(qb) <+ transition( state ? vl : vh, td, tt ); $bound_step(1p); end endmodule
Code for the OR gate is as follows: `include "constants.vams" `include "disciplines.vams"
module aor (out, in1, in2);
output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals
analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 0; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; $bound_step(1p); V(out) <+ transition( ((V(in1) > vth) || (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule
Code for the AND gate is as follows: `include "constants.vams" `include "disciplines.vams"
module aand (out, in1, in2);
output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals
analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 0; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; $bound_step(1p); V(out) <+ transition( ((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule
The NOT gate is implemented as a NAND gate whose inputs are both shorted together as one input: The code for the NAND gate is as below: `include "constants.vams" `include "disciplines.vams"
module anand (out, in1, in2);
output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals
analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 0; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; $bound_step(1p); V(out) <+ transition( !((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule
I input a 2.4GHz as input to the module.
I have set MC input as 0 to the module so the module should given an output of divide by 3. OR 800MHz as output.
When I simulate the circuit for 42ns I observe that I get the correct output @ 800MHz.
However, if I run a transient for 4us I observe that the output is incorrect.
Please refer to the attached waveforms for the 42ns and 5us plots.
I have done quite a bit of searching here in this board but only observe that $bound_step is the solution to solve this problem.
However, I have given $bound_step(1p) in the code as you may notice above.
Still, It is of no use and I get incorrect results.
Can someone please help tell me why I observe correct output when tran runs for 42ns and not when it runs for 5us?
Can someone please help me solve this problem?
Thank you.
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