Hi, Joe -
When you comment out the parameter declaration:
Quote: //parameter R2 = 2;
then I would expect the Verilog-A module would not compile, because it doesn't have a declaration of R2:
Quote: I(na, nb) <+ V(na, nb)/R2;
Perhaps your simulator was using the compiled object from before you commented out the declaration?
When you do
Code: parameter R2 = 2;
the value '2' is the default value. I think of Verilog-A working more like a built-in device rather than a subckt; a built-in diode has a parameter IS with a default of 1e-14, and you can't "undeclare" IS in the model and expect
Code:.param IS=2e-14
to have an effect.