Zorro
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Hi everybody,
here is a description of the problem I have. I hope someone can help with a suggestion. It is important to mention that am relatively new to RNM/wreal modeling (RNM=Real Number Modeling)
This is only for testing purposes but I am seeing some unexpected behavior.
I have two different versions of a stimuli block: - one version uses electrical for inout pin vdd - the other version uses wreal for inout pin vdd.
See picture 1.
Here is the code of both stimuli blocks and the table file:
------------------------------------------------------------------------ VERSION USING ELECTRICAL FOR INOUT PIN vdd
`timescale 1ns/1ps `include "constants.vams" `include "disciplines.vams"
module dut2_stim_vams (vcontrol ,vdd, vss, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4);
// Pin Directions output vcontrol, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4; inout vdd, vss;
// Pin Types wreal ana_out1, ana_out2, ana_out3, ana_out4; logic dig_out1, dig_out2, dig_out3, dig_out4; logic reset; electrical vcontrol ,vdd, vss;
// Variable Declarations real vss_reg; real simtime; real vcontrol_reg; real vdd_reg; reg reset_reg;
// Core
initial begin vss_reg = 0; vcontrol_reg= 0; vdd_reg= 0; reset_reg = 1; #250 reset_reg = 0; end always begin #1 vcontrol_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ; vdd_reg = $table_model($abstime,"vdd_stim.vat","1LL") ; //vdd_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ; end
//always begin //#1000 $finish; //end
analog begin V(vdd) <+ vdd_reg; V(vcontrol) <+ vcontrol_reg; V(vss) <+ vss_reg; end assign reset = reset_reg;
endmodule
------------------------------------------------------------------------
VERSION USING WREAL FOR INOUT PIN vdd
`timescale 1ns/1ps `include "constants.vams" `include "disciplines.vams"
module dut2_stim_vams (vcontrol ,vdd, vss, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4);
// Pin Directions output vcontrol, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4; inout vdd, vss;
// Pin Types wreal ana_out1, ana_out2, ana_out3, ana_out4; logic dig_out1, dig_out2, dig_out3, dig_out4; logic reset; //electrical vcontrol ,vdd, vss; wreal vcontrol ,vdd, vss;
// Variable Declarations real vss_reg; real simtime; real vcontrol_reg; real vdd_reg; reg reset_reg;
// Core
initial begin vss_reg = 0; vcontrol_reg= 0; vdd_reg= 0; reset_reg = 1; #250 reset_reg = 0; end always begin #1 vcontrol_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ; vdd_reg = $table_model($abstime,"vdd_stim.vat","1LL") ; //vdd_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ; end
//always begin //#1000 $finish; //end
// analog begin // V(vdd) <+ vdd_reg; // V(vcontrol) <+ vcontrol_reg; // V(vss) <+ vss_reg; // end
assign vdd = vdd_reg; assign vcontrol = vcontrol_reg; assign vss = vss_reg;
assign reset = reset_reg;
endmodule
------------------------------------------------------------------------
vdd_stim.vat
# time voltage 0 2.5 1u 2.4 2u 2.1 3u 2.0 4u 2.5 5u 2.0
------------------------------------------------------------------------
If a simulate the stimuli blocks alone (without connecting them to any other block) I get the expected behaviors. See picture 2.
Now if I connect a DUT (simple resistor voltage dividers which divide the input voltage by 2 and by 4) the electrical signal behaves correctly (as before) but the wreal signal behaves very strange, its value decreases. See pictures 3, 4, 5 and 6 below.
Any idea what could be causing this wrong behavior in the wreal vdd signal?
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