Hi all,

I wonder whether is it possible to simulate a Verilog HDL code (digital block) without any manipulation with ams simulator? I did a simple simulation as you see in the attached pictures, however after simulation it seems that the outputs are something not well defined! Do I need to define any discipline or add extra lines inside the block code to make the simulation possible? Actually I don't want to make big changes inside my original HDL code:)!
the Verilog hdl code inside the digital block is:

module testofhdl ( co, sum, a, b, ci, clk );
//Input declaration
input a, b, ci,clk;
//Ouput declaration
output co, sum;
//Port Data types
reg co, sum;
always @ (posedge clk)
assign {co, sum}= a+b+ci;
endmodule


Regards,

Medya