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how loop delay in charge pump pll will affect its loop stability (Read 3671 times)
rfic
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how loop delay in charge pump pll will affect its loop stability
Jul 13
th
, 2015, 9:52pm
if i insert a fix loop delay inside CPPLL, how the loop stability suppose to change?
for example, my vco has 8 phases, if i choose phase <7> instead of phase <0>, is loop stability same?
thanks
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loose-electron
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Re: how loop delay in charge pump pll will affect its loop stability
Reply #1 -
Jul 16
th
, 2015, 4:03pm
please clarify your question - a fixed delay on a PLL removes phase margin from the control system, but you mention tapping off of a different connection on a ring oscillator which is something different -
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rfic
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Re: how loop delay in charge pump pll will affect its loop stability
Reply #2 -
Jul 18
th
, 2015, 11:41am
loose-electron wrote
on Jul 16
th
, 2015, 4:03pm:
please clarify your question - a fixed delay on a PLL removes phase margin from the control system, but you mention tapping off of a different connection on a ring oscillator which is something different -
i did mean fix delay, and i think fix delay will degrades PM as well; if this is true, then i expect using phase 7 of ring osc suppose to have less PM compared to using phase 0 of that ring osc as feedback clock -- is this derivation correct?
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loose-electron
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Re: how loop delay in charge pump pll will affect its loop stability
Reply #3 -
Jul 19
th
, 2015, 1:41pm
fixed delays can be introduced at several places in a PLL, in some locations it introduces a phase relationship shift and in other places it changes the phase margin
define what you are doing
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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
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baohulu
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china
Re: how loop delay in charge pump pll will affect its loop stability
Reply #4 -
Jul 23
rd
, 2015, 11:44pm
it seems phase7 and phase8 leave the same phase margin
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