neoflash
Community Fellow
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Mixed-Signal Designer
Posts: 397
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I am simulating a 2-phase (sample and hold) switched capacitor circuit used in pipelined ADC front end.
I have seen method of using timedomain mode in pnoise and calculate the noise in sample phase and hold phase separately.
I have also set it up in source mode and observe the total noise at output. I am curious that what is the noise result I get from this simulation and how is it comparing to the result in timedomain method?
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