neoflash
Community Fellow
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Mixed-Signal Designer
Posts: 397
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Hi,
I have a question about simulating the noise of a S/H circuit.
The method I am using right now is to simulate noise in sample and hold phase separately.
First, I put it in sample mode and simulate the noise over the sampling capacitor (CS) and hold capacitor (CH).
I used HSPICE .NOISE and integrated over entire frequency band. The result seems to match KT/C closely.
However, later I added a switch as noted in the diagram (represented by the red resistor Rp). If I use the noise voltage across capacitor + Rp, the noise is much higher. Rp contributes a lot of noise at higher frequency.
And I think I should use the noise voltage across the capacitor Cs only since it is the charge noise that we care.
Shall I include Rp in sample phase noise integration? Thanks!
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