Hi all,

First: I'm new and not sure which forum is better for this question, hence the crosspost.

Looking for some thoughts on some persistent XOR gate output jitter I am experiencing.  Taking a beating.  The basics:

- quadrature square waves @ ~34kHz from a 2-circuit PPOP comparator IC are driving the PPOP XOR gate inputs
- little/no deterministic jitter is seen in these 2 outputs / inputs to the XOR gate (distribution of HI and LOW pulse widths and period are approximately Gaussian with low variance)
- very clear jitter seen on XOR gate output (2 very distinct clusters in histogram of LOW pulse widths; HI pulse widths are Gaussian with small variance)
- No amount of supply bypassing on either the XOR or the comparator circuit would so much as affect the jitter
- the XOR gate output edge whose phase jitters is the LOW-HIGH transition.  At the time of this edge, one of the quadrature square waves is also transitioning either H-L or L-H.
--- the shorter of the two low pulse widths happens when the one quadrature square wave is also transitioning L-H, and the longer of the two low pulse widths happens when the input is transitioning H-L.  Assuming the issue is VCC or GND movement and the true switching threshold occurs at a fixed point between the VCC and GND as seen at the device, this would make sense.  However, the lack of effect of supply bypassing puts a hole in this theory.

What are the odds that what I'm seeing is layout related / direct electromagnetic coupling between the traces rather than VCC / GND bounce?  If this is the case are there any techniques I could try before waiting for a layout revision?

Thanks in advance for thoughts / advise.