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The Designer's Guide Community Forum › Modeling › Behavioral Models › a error about the 'always' process of verilog-a

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a error about the 'always' process of verilog-a (Read 3038 times)

Big Data New Member Offline Posts: 1	a error about the 'always' process of verilog-a Jan 19^th, 2016, 8:06am does anyone know how to solve this error?(i'm using hspice2010): pvaE* Not support Verilog-D syntax!!! 'always' file "adc.va", line# 14 always @(posedge clk)begin
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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: a error about the 'always' process of verilog-a Reply #1 - Jan 19^th, 2016, 10:04am always is part of Verilog-AMS (or digital Verilog); it is not supported in Verilog-A. You could try using the cross event @(cross(V(clk) - vth)) begin
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AMS_ei Community Member Offline Posts: 67	Re: a error about the 'always' process of verilog-a Reply #2 - Aug 6^th, 2016, 7:43am you can also use @(above(expr)) statement. Thanks.
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