deltasigmaADC wrote on Apr 29th, 2016, 3:12am:Problem comes when I use some verilogA blocks to implement the SAH or replacing the VCCS.
I still couldn't figure out why verilogA is giving me wrong result.
Show me Verilog-A code of SAH.
I think your Verilog-A model has hidden states.
However you specify "(* instrument_module *)" or "(* ignore_state *)" in it.
See
http://www.designers-guide.org/Analysis/hidden-state.pdfCompare the following two models.
http://www.designers-guide.org/VerilogAMS/functional-blocks/sh/sh.vahttp://www.designers-guide.org/VerilogAMS/rf-models/sh/sh.vadeltasigmaADC wrote on Apr 29th, 2016, 3:12am:for getting NTF i usually get the closed loop impulse response and take FFT of it.
Do you mean broad band white spectrum drive instead of single-tone drive ?
V(z) = STF(s)*U(s) + NTF(z)*E(z)
For evaluation of STF, U(s)=1, E(z)=0.
For evaluation of NTF, U(s)=0, E(z)=1.
Right ?
deltasigmaADC wrote on Apr 29th, 2016, 3:12am:I found it helpful to use closed loop response for getting NTF and STF than open loop since it was giving me more accurate results.
I don't think so.
As far as we can not reflect actual waveform of DAC, both NTF and STF are far different from actual situation.
So close loop simulation is too expensive for evaluation of NTF and STF, if you use Sample-Hold circuit(Zero-Order-Hold) instead actual DAC.
BTW, I don't use PSS/PAC for designing CT-DSM-ADC at all.
I use only Transient Analysis with sweeping frequency of single-tone.
Or with two tones drive.