ic_engr
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Hello
I am trying to generate Verilog netlist from schematic in IC 6.1 using NC-Verilog.
I am getting the following errors:
*Error* evalalias: a macro must be defined before its use - (hnlSetOutputVars)
In the Netlist Set-up I am setting stop view as "symbol" since I dont want it to netlist transistors.
Any idea what may be causing this.
Regards ic_engr
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