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Generating Verilog netlist from Schematic in IC61 using NC-Verilog (Read 2373 times)
ic_engr
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Generating Verilog netlist from Schematic in IC61 using NC-Verilog
Jun 16th, 2016, 9:23am
 
Hello

I am trying to generate Verilog netlist from schematic in IC 6.1 using NC-Verilog.

I am getting the following errors:

*Error* evalalias: a macro must be defined before its use - (hnlSetOutputVars)

In the Netlist Set-up I am setting stop view as "symbol" since I dont want it to netlist transistors.

Any idea what may be causing this.

Regards
ic_engr
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Andrew Beckett
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Re: Generating Verilog netlist from Schematic in IC61 using NC-Verilog
Reply #1 - Dec 29th, 2016, 2:07am
 
This was a bug which was fixed in IC617, and happened if you used ADE first and then the Verilog netlister later within the same session. See https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000005xHB5EAM&p...

Regards,

Andrew
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