Hi,
I'm new to veriloga. I'm trying to make a veriloga model for a one-shot circuit. The steady output will be low. It would trigger on both positive and negative edges of input and the output will stay high for a defined "pw" parameter.
I can't figure out how to code the output getting back to steady state after "pw" time has passed after an edge occurs in input.
Here's the code I've written so far.
Code:// VerilogA for scratch_veriloga, oneshot, veriloga
`include "constants.vams"
`include "disciplines.vams"
module oneshot (trigger, oneshot);
input trigger;
output oneshot;
voltage trigger, oneshot;
parameter real vil = 0.5;
parameter real vih = 2;
parameter real thres = (vil+vih)/2;
parameter real vol = 0;
parameter real voh = 2.5;
parameter real td = 0.1n from [0:inf);
parameter real tt = 0.1n from [0:inf);
parameter real pw = 3u from [0:inf);
//parameter integer dir = +1 from [-1:+1] exclude 0;
real state;
analog begin
@(cross(V(trigger)-thres)) state = 1;
//can't figure out how to code that 'state' will go back to 0 after 'pw' time after cross event.
V(oneshot) <+ transition(state?voh:vol,td,tt);
end
endmodule
Could anyone please tell me how I can do this? Or point me to an example?
Thanks.