ana2
Junior Member
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Posts: 10
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Hi everyone
I have some questions about Verilog-A hidden state. In usual transient simulation, Verilog-A hidden state is not a problem. But in PSS simulation, simulation fails if hidden state exist because of syntax check. Can anybody tell me why transient simulation is OK and PSS fails if hidden state exist? Maybe algorithm of transient simulation and PSS simulation is different. I will be appreciate if anybody can tell me some details.
Best regards
ana2
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