nobody
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I guess what you mean by 1 sigma is the random variation due to current mirror mismatch. Now let's think what would lead to more mismatch? If I had a very high gm, an difference in Vth between the mirror transistors will result in high current mismatch.
So the aim is "KILL THE GM"
Above stands from point 1 to point 3.
Maintaining high W and L is a way to achieve lower mismatches in general. But pertaining to current mirror, increasing the L will improve the mismatch numbers and reduce random variations. If you assume square law, it is possible to prove that the mismatch only depends on L for a current mirror and it's inversely. But increasing the overall size is obviously going to reduce the Vt mismatch and effectively your current mismatch. For a given Vt mismatch, you will always find increasing length is the better option. Above all, Vt itself is a function of length. So all this is to be not taken for granted, because it might be that your Vt is very large that is helping you from mismatch for a particular length. I know that increasing L will improve Vt mismatch. But from point 4 and 5, I only increase width and the mosfet is in subthreshold region with 16W. In this subthreshold region, the mismatch is improved. This is what i do not get it
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