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design consideration for a low noise dynamic comparator with preamp. (Read 5789 times)
yvkrishna
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design consideration for a low noise dynamic comparator with preamp.
Mar 12th, 2017, 10:46pm
 
Hi,

I need to design a low noise ~10uVrms inp ref. dynamic comparator working at few 10s of khz.

due to low offset requirement it already employs auto zeroing which can help with flicker noise reduction also.(from preamp stage)

I also need to have a preamp for kickback reasons.

Having aout 40dB gain in preamp almost kills the noise from latch when input referred.

This leaves me no other option rather than burning power in the preamp stage to improve the thermal noise which  gets double sampled and aliased due to sampling operation.

Though the latch speed required is low enough and there is further scope to reduce noise from it I am limited by preamp noise,  so is there any other circuit technique/solution to overcome this ?


Thanks,
yvkrishna



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deba
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #1 - Mar 13th, 2017, 6:06am
 
Are you using a continuously on preamp, or a switchable dynamic preamp? Dynamic preamp can help in reducing the power.
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yvkrishna
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #2 - Mar 13th, 2017, 7:02am
 
Deba,

Since its an active load single stage preamp(diff o/p) of  gain about 40dB, it needs sc-cmfb loop in the phase while reference is sampled.

Not sure what is dynamic preamp ..please point me to any reference link/paper.


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yvkrishna
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ULPAnalog
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #3 - Mar 13th, 2017, 1:59pm
 
You may want to have a look at this paper for dynamic preamp and comparator.

A 26$\ mu $ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios, by Pieter Harpe et al.
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DanielLam
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #4 - Mar 13th, 2017, 3:04pm
 
1) Try using resistors instead of diode-connected loads, they should have less noise than diode-connected loads (note you might need to distribute the gain too).

2) You need to burn power to have low noise.
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yvkrishna
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #5 - Apr 18th, 2017, 9:11am
 
ULPAnalog,

I am evaluating dynamic preamp based comparator which you suggested in the paper. (also attached here)

since larger the integration time window -better the noise, the approach was to slow the overall latch speed to hit such a tight noise spec.

I kept increasing width of input pair and beyond a point I had to put large caps ~20pF at drains of input pair (FN/FP in the diagram) to slow it down further.


Does anyone see any potential issues with this approach to improve noise ?

Rgds,
yvkrishna








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DanielLam
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #6 - Apr 18th, 2017, 10:51am
 
Area, and perhaps comparator speed in the fast and slow corners. The fast corner probably limits your noise. The slow corner limits your speed.
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DanielLam
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #7 - Apr 18th, 2017, 10:53am
 
Oh, I forgot, the comparator input capacitance variation. For an ADC I worked on, I couldn't make the input widths larger than a certain point because the input capacitance varied too much.
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yvkrishna
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #8 - Apr 18th, 2017, 11:09am
 
Daniel,

Thanks for the response.

Huge area ofcourse but there seems to be no other known option/design solution in literature to explore further.

Yes fast corner is bad for noise and need to increase cap further here,speed no concerns here as its low freq application.


Just to get a feel regd input gate cap variation, how large was the w/l  ( I know its very specific to process used)
And what might be the device level reason for this ?


Thanks,
yvkrishna.



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ULPAnalog
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #9 - Apr 19th, 2017, 2:10am
 
You may also reduce the noise by reducing the aperture bandwidth by making the clock transition slower.
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DanielLam
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #10 - Apr 19th, 2017, 1:43pm
 
For comparator input cap variation, it is w*l, not w/l. You should sim it to see as it depends on input voltage as well.

The cap is due to the intrinsic cap of a mosfet.

Another thought I had was with a large device, you also get more input kickback when the comparator latches.
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ULPAnalog
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #11 - Apr 20th, 2017, 1:28am
 
Quote:
Another thought I had was with a large device, you also get more input kickback when the comparator latches.


That is a big problem when you have only latched comparator with no preamp. In this case, preamp should be able to mitigate some of the kick back by isolating the input from the nodes that see the kickback (the output nodes of the preamp). Of course, it can still be a problem for high resolution applications.
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Frank_Heart
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Re: design consideration for a low noise dynamic comparator with preamp.
Reply #12 - Nov 16th, 2017, 2:47pm
 
Hi, yvkrishna,

  If you use a dynamic latch, the integration time matters for noise reduction. All your choices would be 1) bigger input gm 2) bigger drain cap 3) higher voltage level for FN/FP.  

  For 1) you could use bigger input devices, or use PMOS&NMOS input pair, then pull down FN/FP then pull up them to longer the integration time.  
For 3), you can use higher supply for 1st stage, or use two flying cap to boost FN/FP to higher voltage before firing the CLK.

  And I usually saw people using this kind of latch in high speed ADC, with noise level around 100~200uV.  SNDR~70dB.

  For your application, I guess you should use preamp+latch. Otherwise, as ULPAnalog mentioned, large input dependent cap could limit your THD below 80dB.

-Frank
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