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Architectures of CDR in the SerDes IC (Read 1035 times)
SnD
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Architectures of CDR in the SerDes IC
Mar 21st, 2017, 12:49am
 
Hello,
What CDR architecture used in IC tlk1221 or other IC's of this series? I have a hunch that is a blind oversampling, but this not very clear from documentation. In chips of this series used any frequency extraction of the clock or they can only align phase of the multiplied reference clock? If i use this chip only for receiving do i still need reference clock?
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