The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 4:29am
Pages: 1
Send Topic Print
Post-layout simulation of sigma-delta modulators "error" (Read 831 times)
PCCDA
New Member
*
Offline



Posts: 2
Brazil
Post-layout simulation of sigma-delta modulators "error"
Aug 23rd, 2018, 2:08pm
 
Hello,

I am designing a low-voltage SD modulator and I am having some troubles in post-layout simulation. I have performed the layout extraction with assura (RC - decoupled capacitances) and during the simulation (spectre with APS++ in conservative mode), the output DC level of the third active-RC integrator (there are only 3 integrators in the loop filter) did not set correctly, as can be seen in the attached figure. However, to my surprise, I tried the RC extraction setting the "coupled" capacitance option and the circuit works fine (the simulation time has increased as expected).

I already checked the CMFB loop stability and cannot see any problem. All schematic simulations, including PVT corners worked. Post-layout simulations before the top-level routing also worked well with RC extraction in decoupled capacitances mode.

Has anyone ever experienced a similar issue like this?

Regards.
Back to top
 

result_SDM.png
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.