Hi.

I have been trying to carry out mixed mode AMS simulation. For the schematic, I chose a verilog coded or gate, whose output is connected to veriloga coded xor gate and xor output goes to analog inverter (one using nmos and pmos).

At two inputs of Verilog OR Gate I give two different vpulse with V0 as 0.85V and V1 as 0V and tr tf period as required. I am using connectlib ConnectRules18Vfullfast as interface.
XOR gate and Inverters are working as expected but verilog coded OR gate is not showing any transition at output. It is always at level 0. When I replace OR with verilog Inverter in same schematic, it all works fine.

What could be the reason, how do I get correct output from verilog OR? Is there something to do with connec rules?

Image shows the case where 1st and 2nd waveform is input to OR and third waveform is output which doesnt show any transition.