I m trying to make a current mode logic latch at high speed around 8 GHz. The problem is that if i use separate bias at bottom, as shown in the figure, I dont get proper function, as the output voltage of one end remains at vdd/2 which should perhaps go down to zero. I dont know why is the problem. Is it due to wrong sizing of the cross coupled pair.
For the circuit shown, I chose bottom current source to be 30micro A, R =10k. so the total voltage swing during is vdd - VDD-(I*R) ie 900mv - 600mv. when clk bar becomes high, the cross coupled pair must make the circuit go to logic level 1 and 0 but here its moves to a common mode value of the output voltage ie to voltage around 750m , both the output level. Can anyone tell me exact reason for it
is there any tutorial on how to size CML circuits . I attach the image of the circuit which I Implement.