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Oct 14th, 2019, 1:30pm
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OTA Closed loop Simulation (Read 212 times)
kingdarius
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OTA Closed loop Simulation
Jul 01st, 2019, 7:11pm
 
Hi everyone,
I have an OTA that works perfectly in open loop configuration. It is a PMOS input Folded Cascode OTA with open loop gain of 60dB and load capacitance of 20p. The input CMR is 450m-750m. The common mode voltage of Vin and Vref is 600mV normally. The DC level of the output is 600mV. When there is no C1 in the circuit, the two input DC levels of OTA are 600mV but when I add C1 capacitors, this value changes to 950mV. So when I add capacitances C1, the OTA performance degrades significantly, because of the DC voltage of the OTA input changes.  The closed loop configuration is attached. Can anyone suggest why is it so and what should I do to fix this? In addition to that, can anyone suggest a good reference for OPAMP and OTA test benches?

Thanks
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kumar.g
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Re: OTA Closed loop Simulation
Reply #1 - Jul 30th, 2019, 12:29am
 
When you add C1, it blocks the DC. Your input common mode is anyhow blocked.
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Horror Vacui
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Re: OTA Closed loop Simulation
Reply #2 - Aug 12th, 2019, 6:44am
 
An amp with 60dB gain should be simulated together with its feedback loop.  You will save lots of headaches caused by wrong DC level at the output.
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