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Offset cancellation in switched capacitor circuit (Read 365 times)
vm511
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Offset cancellation in switched capacitor circuit
Jul 10th, 2019, 12:47pm
 
I was trying to use a capacitive reset switched capacitor amplifier so as to also have offset cancellation. However, I observe that as I keep decreasing the clock rate, the offset sampled starts increasing. It's not very clear to me how the clock rate would impact the offset sampled at the output since the cancellation in based on charge conservation. The feedback capacitors I am using are very small (50fF)
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subtr
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Re: Offset cancellation in switched capacitor circuit
Reply #1 - Dec 13th, 2019, 6:34am
 
if you can upload a circuit diagram of what you're doing it would be the best. Are you doing the below?

https://www.google.com/url?sa=i&source=images&cd=&ved=2ahUKEwiilvP367LmAhVHyDgGH...
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vm511
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Re: Offset cancellation in switched capacitor circuit
Reply #2 - Dec 13th, 2019, 6:44am
 
Hi,
The issue had gotten resolved.
Thanks!
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