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Jul 2nd, 2022, 10:48am
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LDO Simulation Output Results (Read 626 times)
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LDO Simulation Output Results
Aug 20th, 2019, 4:37pm
I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

I set the reference voltage to about 650mv and did a DC simulation.

The regulated voltage starts up and then dies as the VDD is ramped up.

What could be causing this ?

Thank you.
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Horror Vacui
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Posts: 119
Dresden, Germany
Re: LDO Simulation Output Results
Reply #1 - Aug 30th, 2019, 6:49am
Exchanged input terminals in an opamp could do that. The PMOS gate goes to supply and no current is flowing through the pass transistor. The load will discharge the output.
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