The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Sep 17th, 2019, 3:49pm
Pages: 1
Send Topic Print
LDO Simulation Output Results (Read 96 times)
repah
Community Member
***
Offline



Posts: 43

LDO Simulation Output Results
Aug 20th, 2019, 4:37pm
 
I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

I set the reference voltage to about 650mv and did a DC simulation.

The regulated voltage starts up and then dies as the VDD is ramped up.

What could be causing this ?

Thank you.
Back to top
 

LDO_001.png
View Profile   IP Logged
Horror Vacui
Community Member
***
Offline



Posts: 88
Germany
Re: LDO Simulation Output Results
Reply #1 - Aug 30th, 2019, 6:49am
 
Exchanged input terminals in an opamp could do that. The PMOS gate goes to supply and no current is flowing through the pass transistor. The load will discharge the output.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2019 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.