The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jan 22nd, 2020, 12:12am
Pages: 1
Send Topic Print
Scaling of Sampling clock in CT-SDM ADC (Read 53 times)
neoflash
Community Fellow
*****
Offline

Mixed-Signal
Designer

Posts: 387

Scaling of Sampling clock in CT-SDM ADC
Jan 02nd, 2020, 4:23pm
 
If I want to optimize for area, does it make sense to push the sampling clock the higher end?

Assuming SQNR is sufficient, and output sample rate is fixed. If I double Fs, I can shrink integrator Cap by 2x.

Other performances:

- Noise is not changing as R/gm doesn't really change
- OSR is 2x but little impact on perf as Q noise is small
- excess delay can be compensated

any other item that I missed? Thanks.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2020 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.