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Why SPI chip select signal is active low? (Read 1312 times)
neoflash
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Why SPI chip select signal is active low?
Jan 06th, 2020, 9:04am
 
Is this an arbitrary choice or has some electrical reason behind it?

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Neo
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Frank Wiedmann
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Re: Why SPI chip select signal is active low?
Reply #1 - Jan 8th, 2020, 7:39am
 
A quick search turned up this on https://electronics.stackexchange.com/questions/7664/why-are-things-like-reset-m...:

Wikipedia says (http://en.wikipedia.org/wiki/Logic_level):

Many control signals in electronics are active-low signals (usually reset lines, chip-select lines and so on). This stems from the fact that most logic families can sink more current than they can source, so fanout and noise immunity increase. It also allows for wired-OR logic if the logic gates are open-collector/open-drain with a pull-up resistor. Examples of this are the I²C bus and the Controller Area Network (CAN), and the PCI Local Bus. RS232 signaling, as used on some serial ports, uses active-low signals.
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