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May 28th, 2020, 11:44pm
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The problem of special bus definiton of veriloga (Read 153 times)
Bisharp
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The problem of special bus definiton of veriloga
Apr 20th, 2020, 1:40am
 
Hello everyone, I met a problem about bus definiton as following;
There is a specified cell, and the symbol view has a port named "CKS_P<127:0:8>". ->(fig.1)
when I use the option "Create-Cellview-From Cellview" in schematic view, the virtuoso will generate a veriloga template for me. In this template, the port CKS_P is defined as "inout [127:7] CKS_P". ->(fig.2)
Something goes wrong when I click the Check&Save button; Lots of Error is printed in the CIW:
"ERROR: For bus terminal CKS_P<127:7>, port CKS_P<82> is missing in design" ->(fig.3)

I understood why there is an Error, but I don't know how to fix this error without changing the symbol structure, it seems there is no grammer to solve this problem in veriloga. Is there any one have had this problem or can help me.
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Bisharp
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Re: The problem of special bus definiton of veriloga
Reply #1 - Apr 20th, 2020, 1:48am
 
fig2 and fig3
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Geoffrey_Coram
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Re: The problem of special bus definiton of veriloga
Reply #2 - May 1st, 2020, 1:59pm
 
I don't know what this means: "CKS_P<127:0:8>"

It certainly doesn't look like valid Verilog-A syntax. It seems that virtuoso should have dealt with converting it to VA syntax.
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Bisharp
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Re: The problem of special bus definiton of veriloga
Reply #3 - May 6th, 2020, 5:23am
 
Thank you for your reply, Geoffery,
CKS_P<127:0:8> is valid in schematic and symbol view in virtuoso,  which represent CKS_P port with 16 bits width (127, 119, 111, 103, 95, 87, 79, 71, 63, 55, 47, 39, 31, 23, 15, 7). if possible, you can draw a schematic in this way;
The problem lies exactly at the place that when i use "Create-Cellview-From Cellview" in schematic view,  the virtuoso could not convert this format correctly in VA Sad
The result of converting is "inout [127:7] CKS_P" in figure2, which has 121 bits width, and the VA check&save failed.

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Andrew Beckett
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Re: The problem of special bus definiton of veriloga
Reply #4 - May 12th, 2020, 12:30am
 
You should report this to Cadence Customer Support. I think it would have to be handled by splitting the bus in the Verilog-A model as I'm not sure there's syntax to represent this sliced bus in this way in Verilog/Verilog-A without expanding the bits, but either way this should be handled more gracefully by the cellView to cellView capability in Virtuoso.

Regards,

Andrew.
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Bisharp
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Re: The problem of special bus definiton of veriloga
Reply #5 - May 12th, 2020, 1:02am
 
Thank you for your reply, Andrew

I don't have a clear understanding of "cellview to cellview capability in virtuoso", in my view, I just used virtuoso to convert the schematic view into va view as figure 2, which is wrong;

And I also try a lot way to use sliced bus in verilog-A by hand, all fails in grammer..
I will report this in cadence support.

Regards,
Ying

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