alexshel44
New Member
Offline
Posts: 2
Calgary
|
Hello Everyone,
I am working through the book 'The Designer's Guide to Verilog-AMS' in chapter 3 listing 26 there is a model for an ideal ADC. I fully understand the code however I am having difficulties generating a symbol view in Virtuoso due to variable number of bits. If I instead set the number of bits to a constant everything seems to work properly.
When I generate the symbol view with the variable number of bits it gets an error on the output bin which is defined as out<0:bits-1> where bits is a variable.
Does anyone have any advice for how I can get this to work?
I'm not sure what versions are relevant but, I am using Virtuoso 6.1.7.
Thanks a lot,
Alex
|