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Dec 9th, 2022, 7:11am
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Modelling MOS gate cap variation with VGS voltage in transient (Read 374 times)
mohan
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Modelling MOS gate cap variation with VGS voltage in transient
Feb 25th, 2022, 1:31am
 
Hi All

I want to model the MOS gate cap variation with VGS voltage in transient domain. Means lets say when the VGS changes abruptly bringing the MOS from OFF state to ON state ( subthreshold or full inversion) I see in simulations the gate cap is changing instantly which I doubt wont be the case. At least while going from OFF to subthreshold I expect there should be some time constant involved between VGS variation and the gate cap change as the channel inversion charge comes mostly from its bulk which are minority carriers.

1) Is my understanding correct?    
2) How can I model this effect ?
3) Is there a way to check this behavior on silicon for a MOS?

Thanks in advance for any feedback/suggestions on this topic
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Maks
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Re: Modelling MOS gate cap variation with VGS voltage in transient
Reply #1 - Mar 17th, 2022, 12:19pm
 
Your understanding is not correct.

Carriers in the inversion layer come not form the the substrate (as minority carriers), but from source / drain easily doped regions, which is as very fast process - of the order of transit time, probably ps range (of course, depends on gate lengths etc.).

But another questions is - are you doing SPICE simulations?
If so, your results depend on what's included into the SPICE model.
I think she "non-quasi-static" effects are included in the latest SPICE models, but I am not sure how accurate those models are, and - whether that result matters for you or not.
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