Hello All,
there is a similar thread covering this, but using veriloga/verilogams:
https://designers-guide.org/forum/YaBB.pl?num=1629723383Now I would like to implement the same but using wreal only (or systemVerilog) i.e. I cannot use the @timer function.
If the clock doesn't toggle then the frequency should become zero after a duration that is longer than the period of the lowest frequency that is expected.
What is the best way to implement this?
I am using the code below as a starting point. Thank you very much!
// MEASURE ACTUAL DIGITAL FREQUENCY:
real fdig,tupd=0;
// on leading clock edge
always @(VCO_OUT) begin
// compute F=1/period (Hz)
if (tupd>0) fdig=1e9/(($realtime-tupd)*2);
tupd = $realtime; // and save edge time
end