The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Oct 2nd, 2022, 3:16am
Pages: 1
Send Topic Print
Frequency Measurement when clock is constant (wreal) (Read 50 times)
amsrc
New Member
*
Offline



Posts: 8

Frequency Measurement when clock is constant (wreal)
Sep 20th, 2022, 8:03am
 
Hello All,

there is a similar thread covering this, but using veriloga/verilogams: https://designers-guide.org/forum/YaBB.pl?num=1629723383

Now I would like to implement the same but using wreal only (or systemVerilog) i.e. I cannot use the @timer function.

If the clock doesn't toggle then the frequency should become zero after a duration that is longer than the period of the lowest frequency that is expected.

What is the best way to implement this?

I am using the code below as a starting point. Thank you very much!


// MEASURE ACTUAL DIGITAL FREQUENCY:
real fdig,tupd=0;  

// on leading clock edge
always @(VCO_OUT) begin
 //  compute F=1/period (Hz)
 if (tupd>0) fdig=1e9/(($realtime-tupd)*2);
 tupd = $realtime; //   and save edge time
end
Back to top
 
 
View Profile   IP Logged
amsrc
New Member
*
Offline



Posts: 8

Re: Frequency Measurement when clock is constant (wreal)
Reply #1 - Sep 20th, 2022, 8:10am
 
Please see attached picture.
Back to top
 

freq_meas.PNG
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2349
Silicon Valley
Re: Frequency Measurement when clock is constant (wreal)
Reply #2 - Sep 20th, 2022, 9:22am
 
Here is how I have implemented this idea in Verilog-AMS.
//determine frequency of output
Code:
always @(posedge out) begin
    t = $abstime;
    freq = 1.0/(t – prev);
    prev = t;
    disable oscDead;
end

// if no crossing for a while, assume oscillator is dead
always begin : oscDead
    #(100n) freq = 0;
end 



Notice that the first always block triggers on posedge out.  You don't have the posedge, so you are measuring the half-period rather than a full period.  You approach will not work well on non-symmetric waveforms.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
amsrc
New Member
*
Offline



Posts: 8

Re: Frequency Measurement when clock is constant (wreal)
Reply #3 - Sep 26th, 2022, 8:57am
 
Thank you very much for your answer Ken!

You are right when you say that the approach using

   always @(VCO_OUT) begin

will not work well on non-symmetric waveforms. This approach assumes a 50% duty cycle which is not necessarily the case.

Therefore I followed your suggestion of using the posedge.

I tried implementing your approach and it is working almost fine.

The real variable "freq" becomes 0.0 when we have a period longer than e.g. 40ns.

The only problem is that as soon as VCO_OUT goes high again the frequency will be re-calculated immediately with the values of variables "t" and "prev" because these values were not "reseted". See picture below.
Back to top
 

freq_meas_02.PNG
View Profile   IP Logged
amsrc
New Member
*
Offline



Posts: 8

Re: Frequency Measurement when clock is constant (wreal)
Reply #4 - Sep 26th, 2022, 9:01am
 
To solve the issue mentioned in the previous reply the variable "prev" was also "reseted" to 0.0.
Additionaly the freq is calculated only if "prev" is greater than 0.0.
With this modification I am getting the expected results. See picture below.

Again, thank you very much for your help. I see now how disabling the block implements what the @timer function was doing in veriloga.
Back to top
 

freq_meas_03.PNG
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2022 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.