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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Workaround for using systemVerilog type #delay
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Workaround for using systemVerilog type #delay (Read 376 times)
mikev
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Workaround for using systemVerilog type #delay
Nov 30th, 2022, 9:13am  
Is there a work around for using systemVerilog type delays in veriloga-ams?

For example, in sv:
#1us
#1ms
#1ns

Is there a way to do this in vams?

Thanks in advance.
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Ken Kundert
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Re: Workaround for using systemVerilog type #delay
Reply #1 - Nov 30th, 2022, 11:34am  
Set the time unit in the `timescale directive to 1s, then use the scale factor without the units.  For example:

Code:
`timescale 1s/1ps

...

always #50n out = !out;
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