The Designer's Guide Community
Forum
ForumVerilog-AMSAnalysisModelingDesignTheory
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 17th, 2024, 8:33pm
 
  HomeHelpSearchLoginRegisterPM to admin    
The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Workaround for using systemVerilog type #delay
‹ Previous topic | Next topic ›
Pages: 1
Send Topic Print
Workaround for using systemVerilog type #delay (Read 280 times)
mikev
New Member
*
Offline



Posts: 4
Workaround for using systemVerilog type #delay
Nov 30th, 2022, 9:13am  
Is there a work around for using systemVerilog type delays in veriloga-ams?

For example, in sv:
#1us
#1ms
#1ns

Is there a way to do this in vams?

Thanks in advance.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: Workaround for using systemVerilog type #delay
Reply #1 - Nov 30th, 2022, 11:34am  
Set the time unit in the `timescale directive to 1s, then use the scale factor without the units.  For example:

Code:
`timescale 1s/1ps

...

always #50n out = !out;
Back to top
 
 
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
‹ Previous topic | Next topic ›
« Home ‹ Board
The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.