Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Cadence Modelwriter, creating new template	Srikanth	4	4775	Aug 6^th, 2008, 9:39am By: jbdavid
modelling fractional delays in SIMULINK for continuous-time delta-sigma	vivkr	0	3234	Jul 25^th, 2008, 4:59am By: vivkr
behavioural modelling of a VCO for phase noise using Verilog -A	prem	1	524	Jul 21^st, 2008, 2:03am By: Stefan
temperature detector with hysteresis in Verilog-A	boa	1	59	Jul 10^th, 2008, 10:33am By: Geoffrey_Coram
Wrong magintude of Bode plot with Aktas's behavioral model	vence	0	1683	Jun 28^th, 2008, 12:43am By: vence
LDO modeling, nonlinear dynamics	Srikanth	5	1427	Jun 24^th, 2008, 1:19am By: buddypoor
Modeling the Warburg element in Verilog-A	mehregan	3	5639	Jun 17^th, 2008, 5:25pm By: Ken Kundert
Some doubts in modeling jitter	pkd	2	2854	Jun 10^th, 2008, 5:01am By: Visjnoe
Bahavioral model of pipelined ADC	manodipan	1	2608	Jun 3^rd, 2008, 3:42am By: navywhj
verilogA module vs. analoglib module	xiey	2	6042	May 15^th, 2008, 6:57pm By: sheldon
Sigma delta model validation	cdbular	2	3842	Apr 30^th, 2008, 7:02pm By: cdbular
verilog-a model for voltage regulator and bandgap	sonugoyal	2	4738	Apr 29^th, 2008, 4:55am By: Stefan
external supply pins	ScottO	2	2808	Apr 24^th, 2008, 6:05am By: ScottO
Veriloga model of a current limted voltage source	mattpace	6	1649	Apr 16^th, 2008, 4:46pm By: Peruzzi
how to model polyphase filter	Faisal	3	831	Apr 13^th, 2008, 11:22pm By: Stefan
survey paper on behavioral modeling	rajdeep	1	2155	Apr 13^th, 2008, 10:32pm By: jbdavid
*ncelab: W,BIGWBS**	helix	2	3765	Mar 12^th, 2008, 7:30pm By: helix
Modeling DDS/DAC modulator	Faisal	10	8884	Mar 3^rd, 2008, 1:40pm By: Faisal
Moved: spectre transient noise - Started by: Forum Administrator This Topic has been moved to Circuit Simulators by Forum Administrator.
Noise	safwatonline	1	481	Feb 14^th, 2008, 3:54pm By: Ken Kundert

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