Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
VCO glitches in Verilog-A (Hspice)	imtired	1	2543	Jun 21^st, 2007, 10:32am By: Geoffrey_Coram
veriloga model for esd pads	mengm0411	6	1464	Jun 12^th, 2007, 11:03pm By: NKS
Mathcad model fractional pll	dhirajv12	1	3073	Jun 5^th, 2007, 2:13pm By: imtired
Ver AMS Diff Amp Model (esp for HS CML logic gate)	jhjones	3	4363	May 30^th, 2007, 11:32am By: jhjones
Amplifier model in C++ for simulationg in CppSim	fjp@micrel.no	0	2015	May 30^th, 2007, 7:18am By: fjp@micrel.no
capbank vco verilog-a modeling	memnon	2	56	May 29^th, 2007, 8:17am By: Eugene
Behavioral Models: Charge pumps	thamiral	9	9238	May 24^th, 2007, 10:31am By: imtired
Pulse source in Verilog-A(MS)	nvs117	2	3142	May 9^th, 2007, 3:59am By: nvs117
Strange XNOR behavior in veriloga using spectre	naone	1	2557	Apr 16^th, 2007, 3:53am By: Andrew Beckett
How to simulate reference spur of PLL ?	ben-w	1	3712	Apr 13^th, 2007, 8:44pm By: sheldon
Nonideal Opamp Verilog-A Model - tran. analysis	daims	0	5648	Feb 23^rd, 2007, 12:33am By: daims
How to parameterize a string variable	naone	4	4597	Feb 22^nd, 2007, 11:09am By: Andrew Beckett
wrong noisefigure of current mixer in veriloga	Jochen	2	5858	Feb 6^th, 2007, 2:04am By: Jochen
noiseless mixer has 3db NF?	Jochen	2	7323	Feb 6^th, 2007, 1:18am By: Jochen
Re: Upsampler	Geoffrey_Coram	0	1727	Feb 2^nd, 2007, 5:26am By: Geoffrey_Coram
invoking gaussian function in hspice into veriloga	parthsv	1	3310	Jan 28^th, 2007, 4:52am By: ACWWong
Behavioural code for Generating a jittered clock	pkdas	0	1636	Jan 17^th, 2007, 3:23am By: pkdas
noise model of ota	parthsv	6	1333	Jan 17^th, 2007, 3:09am By: Andrew Beckett
Defining both current and voltage at output port?	Saran	3	3654	Jan 16^th, 2007, 6:27am By: Geoffrey_Coram
Plot I-V Curve by Using Matlab	qiushidaren	4	6495	Jan 15^th, 2007, 12:20pm By: mg777

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