Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Determination of Beta value for Standard cell library	Superman	0	373	Feb 20^th, 2013, 2:10am By: Superman
MAx decap value	summi	3	3071	Feb 8^th, 2013, 11:11pm By: Erez_Sarig
Input common mode of Switched Capacitor Integrator	luoshuer	1	3319	Jan 12^th, 2013, 7:08am By: sheldon
CT multi bit sigma delta ADC related	zxliao	0	1338	Jan 6^th, 2013, 1:14am By: zxliao
Do we need a digital filter following a SAR ADC	zrsh001	2	3629	Jan 5^th, 2013, 9:28pm By: sheldon
sampling clock jitter stand for？	880321	1	1806	Jan 2^nd, 2013, 11:05pm By: Virvasav
Moved: ring VCO phase noise is positive - Started by: 880321 This Topic has been moved to RF Simulators by Ken Kundert
8 bit SAR ADC DAC capacitive array!	Sx_cut	1	483	Nov 19^th, 2012, 8:36pm By: loose-electron
Competitive Chip Design - A "must read" for all designers.	loose-electron	4	4281	Nov 14^th, 2012, 4:12pm By: loose-electron
sar adc comparator offset rejection	baohulu	2	3446	Oct 6^th, 2012, 5:40am By: ywguo
Choice of ADCs	Sx_cut	1	1711	Oct 2^nd, 2012, 4:51am By: loose-electron
Sourcing appropriate oscillator	freqout	4	6893	Sep 5^th, 2012, 6:23pm By: freqout
how to handle higher bias current??	raja.cedt	3	2800	Sep 3^rd, 2012, 7:00am By: Lex
Digital filter design for incremental delta-sigma ADC	Berti	1	2431	Aug 21^st, 2012, 8:59pm By: TraceTheLoad
Confused about the Role of N+ and P+ Guard Ring	waosai	2	2627	Aug 18^th, 2012, 7:10pm By: Lynn Lou
The transfer function of a SC integrator	eeBismarck	1	472	Aug 2^nd, 2012, 6:31am By: buddypoor
Understanding DAC SFDR	analog2001	5	5817	Jul 18^th, 2012, 10:50pm By: BackerShu
Question about deterministic jitter	busoni	4	3771	Jul 18^th, 2012, 10:34pm By: BackerShu
pnoise not showing 1/f noise attenuation	analog2000	1	2276	Jul 18^th, 2012, 10:26pm By: BackerShu
Moved: Analysis of Switched Cap Integrator - Started by: analog_design This Topic has been moved to Circuit Simulators by Ken Kundert

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