Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Port pattern matching excitation	ChrisV	0	197	May 10^th, 2013, 6:43am By: ChrisV
ahdl_include filePath	spinfab	2	3117	May 7^th, 2013, 12:52am By: spinfab
Inherited Connections	irfan35	7	2253	May 6^th, 2013, 3:17am By: boe
transformer modeling with leakage inductance	hedaye	2	3551	May 3^rd, 2013, 5:59am By: hedaye
Interpolating From Function	warprider	0	1559	Apr 28^th, 2013, 12:16am By: warprider
Load Resistance of Two-Port	oner	2	988	Apr 25^th, 2013, 2:17am By: oner
Converting integer to string in Verilog-A	Deyan Levski	1	5849	Mar 22^nd, 2013, 7:25am By: Geoffrey_Coram
Single line assignment to multiple variable	Tobben24	3	4328	Mar 20^th, 2013, 9:44am By: Paul Floyd
ADC simulation Verilog A	batmanbeginz	1	4488	Mar 16^th, 2013, 1:15pm By: sourav
need solution for following error in rtl synthesis tool in cadence	aathi27	1	2023	Mar 6^th, 2013, 5:17am By: Geoffrey_Coram
wires to vec in VerilogA	jmith	1	627	Feb 15^th, 2013, 6:09am By: boe
Library section includes in Verilog-AMS?	Chris Atkins	1	2337	Feb 11^th, 2013, 12:34pm By: Geoffrey_Coram
Netlisting failed using Verilog-A block	aliasnikhil	3	9412	Jan 31^st, 2013, 5:57am By: Geoffrey_Coram
Ideal diode model in VerilogA/MS	Dushyant Juneja	6	14630	Jan 28^th, 2013, 9:44pm By: Dushyant Juneja
Verilog-A model Monte Carlo simulation with spectre	yueguoguo	5	6913	Jan 14^th, 2013, 6:05am By: Geoffrey_Coram
gmin or gdev in model using $simparam()	Bob Atwell	4	1941	Jan 11^th, 2013, 11:34am By: Bob Atwell
sformat equivalent in Verilog-A	ShawnR	1	2414	Jan 7^th, 2013, 5:53am By: Geoffrey_Coram
disable task by event handler in same module	RolfK	0	1356	Jan 4^th, 2013, 1:53pm By: RolfK
Bug or nor not a bug in table_model	RolfK	1	2139	Dec 17^th, 2012, 8:03am By: Geoffrey_Coram
TB ground issue?	RolfK	1	1911	Dec 7^th, 2012, 10:25pm By: Ken Kundert

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