Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Ultraedit Wordfile for AMS	RolfK	0	1390	Dec 6^th, 2012, 10:24am By: RolfK
n times fopen read only	RolfK	0	1178	Dec 5^th, 2012, 10:31am By: RolfK
current limiter	fgcsk	10	6377	Dec 5^th, 2012, 4:46am By: boe
Issue with fopen:erase first time through append afterwards	Claude	8	6256	Nov 27^th, 2012, 1:26pm By: Claude
Using $table_model with time as one axis	RolfK	1	4033	Nov 26^th, 2012, 6:30am By: Geoffrey_Coram
Good books to Verilog-A	RolfK	1	2430	Nov 20^th, 2012, 5:47pm By: Ken Kundert
Cannot generate ahdl_include in netlist by ADE	Daniel Lai	0	1637	Oct 31^st, 2012, 4:57am By: Daniel Lai
usage of noise_table	Richardsim	1	1725	Oct 29^th, 2012, 5:57am By: Geoffrey_Coram
Clock generator with variable period in Verilog-A	gsensor	5	8841	Oct 19^th, 2012, 11:52am By: boe
file write	kamath	3	3111	Oct 10^th, 2012, 2:40pm By: Geoffrey_Coram
verilog ams ADC model with PSS	conr	3	4171	Oct 1^st, 2012, 6:30am By: Geoffrey_Coram
Non-uniform sampling in VCO model	TraceTheLoad	4	1357	Aug 30^th, 2012, 9:11am By: TraceTheLoad
instantiation inside analog block?	Go,TB	3	3383	Aug 22^nd, 2012, 7:13am By: boe
Sample and Hold without Hidden State but with External Clock Input	mardukeyo	2	4215	Aug 21^st, 2012, 10:07pm By: mardukeyo
Question about output current in VerilogAMS	urian	9	7492	Aug 1^st, 2012, 10:28am By: Ken Kundert
Verilog A question	MarkG	2	3529	Jul 25^th, 2012, 7:18am By: Geoffrey_Coram
Problems with Monte Carlo Simulation with VerilogA model	yongnali	2	5128	Jul 18^th, 2012, 12:59pm By: boe
I(<vin>) and I(vin,vin)	ywguo	3	3954	Jul 17^th, 2012, 7:08pm By: ywguo
Code level for analog block	fabian	4	1048	Jul 11^th, 2012, 6:17pm By: carlgrace
simulating synthesized verilog digital unit with analog unit	mohammadreza	1	1675	Jul 11^th, 2012, 6:16pm By: carlgrace

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